By Arndt Bode (auth.), Ming Xu, Yinwei Zhan, Jiannong Cao, Yijun Liu (eds.)
We are at the moment witnessing a proliferation in parallel and dispensed processing applied sciences and purposes. besides the fact that, extra new applied sciences have ushered in unprecented demanding situations to the study group around the variety of high-performance computing, multi-core microprocessor structure, networks and pervasive computing, in addition to new paradigm computing concerns. APPT 2007 was once subsidized by way of the China laptop Federation, in cooperation with TCPP of the Institute for electric and Electronics Engineers (IEEE). The hugely confident responses to the former APPT workshops inspired us to proceed this foreign occasion. This 12 months, APPT used to be upgraded to the foreign Symposium on complex Parallel Processing applied sciences. although, it saved its conventional taste by way of sharing of the underlying theories and purposes, and the institution of latest and long term collaborative channels. and it'll proceed to supply a discussion board for researchers, execs, and commercial practitioners from around the globe to file on new advances in high-performance structure and software program, in addition to to spot matters and instructions for examine and improvement within the new period of evolving applied sciences. The luck of APPT 2007 used to be as a result the labor and making plans of a giant staff of popular researchers from world wide, who served at the Technical application Committee and the Organizing Committee. Their valuable efforts in constructing this technical software are so much gratefully said. particularly, we want to thank this system Co-chairs, Xin Chen, Xuejun Yang, and Albert Y. Zomaya.
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Additional resources for Advanced Parallel Processing Technologies: 7th International Symposium, APPT 2007 Guangzhou, China, November 22-23, 2007 Proceedings
The fault-tolerant technology of its subsystem must give attention to the volume & power efficiency of spacecraft and meet the needs of appropriate redundancy and adequate reliability and the commercial request for low cost and high performance of COTS. So we analyzed function and logic structure of the OBC firstly. Secondly, we put forward an embedded design scheme with SEU-tolerant architecture. Finally, its reliability has been validated in theory. In the future, we will carry out the system to be validated in the spatial environment.
Secondly, we put forward an embedded design scheme with SEU-tolerant architecture. Finally, its reliability has been validated in theory. In the future, we will carry out the system to be validated in the spatial environment. References 1. : Research on Realizationof ASIC in Chinese Spacecraft. Chinese Space Science and Technology 5 (2002) 2. : Analyzing SEU Effects in SRAM-based FPGAs. IOLTS2003: IEEE International On-Line Testing Symposium , 119–123 (2003) 3. : Improving FPGA Design Robustness with Partial TMR.
38 H. Ying et al. Fig. 10. 10, the single board was also the mixed combination model. The SEU-tolerant reliability of its modules (concluding Flash and RAM) was represented by Rm (Rm=R1R2), thereinto R1 denoted the reliability of Flash (or RAM) and R2 denoted the arbitrator of FPGA. λ denoted the SEU-invalidation effects, Rf and Rr respectly denoted the reliability of triple-module-redundant system of Flash and RAM, and the reliability of CPU in a single board was denoted by Rcpu. In the thesis, we have supposed that there were not more than one-bit SEU-upset in synchronization, and the invalidation effects of each module in the parallel connection modules was equal.